Full-quantum modeling of III-V Tunnel-FETs architectures

This paper review the device and circuit performance of co-optimized n- and p-type tunnel field-effect transistors (TFETs) integrated on the same InAs/Al0.05Ga0.95Sb platform, using a full-quantum ballistic simulator. Based on 3D full-quantum simulations, the investigated devices feature steep subthreshold slopes and relatively high ON-state currents, and are combined to realize an inverter. Benchmarking against aggressively scaled CMOS logic based on multigate architectures highlights the potential of the proposed TFET implementations to perform up to 10× and 100× faster for IOFF = 5nA/um and 10 pA/um, respectively, at very low supply voltage VDD = 0.25V, for equal levels of static power dissipation. Afterwards, a simulation study on the impact of interface traps and strain on the I–V characteristics is carried out, in order to capture the effect of interface/border traps on the device electrostatics. The effect of an experimental Dit distribution of a high-k gate stack on InAs is investigated. Unfortunately, traps induce a significant reduction of the ON-state current. However, it turns out that localized strain at the source/channel heterojunction caused by lattice mismatch is able to induce a performance enhancement for the n-type TFET, with respect to the ideal device, even in the presence of traps. On the contrary, for the p-type one, a current degradation  18% is observed.

This paper review the device and circuit performance of co-optimized n- and p-type tunnel field-effect transistors (TFETs) integrated on the same InAs/Al0.05Ga0.95Sb platform, using a full-quantum ballistic simulator. Based on 3D full-quantum simulations, the investigated devices feature steep subthreshold slopes and relatively high ON-state currents, and are combined to realize an inverter. Benchmarking against aggressively scaled CMOS logic based on multigate architectures highlights the potential of the proposed TFET implementations to perform up to 10× and 100× faster for IOFF = 5nA/um and 10 pA/um, respectively, at very low supply voltage VDD = 0.25V, for equal levels of static power dissipation. Afterwards, a simulation study on the impact of interface traps and strain on the I–V characteristics is carried out, in order to capture the effect of interface/border traps on the device electrostatics. The effect of an experimental Dit distribution of a high-k gate stack on InAs is investigated. Unfortunately, traps induce a significant reduction of the ON-state current. However, it turns out that localized strain at the source/channel heterojunction caused by lattice mismatch is able to induce a performance enhancement for the n-type TFET, with respect to the ideal device, even in the presence of traps. On the contrary, for the p-type one, a current degradation  18% is observed.

III–V materials heterojunction subthreshold slope interface traps (ITs) quantum transport strain tunnel FETs (TFET)

III–V materials heterojunction subthreshold slope interface traps (ITs) quantum transport strain tunnel FETs (TFET)