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Nanoelectronic Devices

Composants nanoélectroniques




CompoNano - ISSN 2516-3914 - © ISTE Ltd

Aims and scope

Objectifs de la revue

Nanoelectronic Devices covers the following subjects :

 

– FD-SOI Devices
– Multi-Gate devices on bulk or insulator substrates
– 1D Devices (Nanowires, Carbon Nanotubes, etc.)
– 2D channel Devices
– Multi-channel Devices
– Small Slope Switches Devices (Tunnel FET, FeFET, NEMS, etc.)
– Ultra low power Devices
– Nanodevices with alternative channel materials
– Design, technology, integration, modelling, numerical simulation
of Nanoelectronic devices
– Circuit design based on nanoelectronic devices
– Charge-based and non-charge based (PCRAM, RRAM, MRAM)
DRAM, SRAM, and Non-Volatile Memories

Composants nanoélectroniques couvre les sujets suivants :

– Composants FD-SOI
– Composants Multi-Grilles sur substrats de Si massif ou sur isolant
– Composants à base de structures 1D
– Composants à base de structures 2D
– Composants Multi-Canaux
– Composants Small-Slope-Switches
– Composants très faible consommation
– Matériaux alternatifs pour les canaux des composants nanoélectroniques
– Conception, technologie, intégration, modélisation, simulation numérique
et caractérisation des composants nanoélectroniques
– Conception de circuits basés sur les composants nanoélectroniques
– Mémoires Non-Volatiles, DRAM, SRAM basées sur un stockage de charges
ou une variation de résistance (PCRAM, RRAM, MRAM)

Journal issues

2018

Volume 18- 1

Tunnel FETs

Recent articles

Tunnel FETs for ultra low Power Nanoscale Devices

Future ICs are facing dramatic challenges in performance as well as static and dynamic power consumption, which could be overcome using disruptive concepts, device architectures, technologies and materials. Promising (...)


Capturing Performance Limiting Effects in Tunnel-FETs

In this paper a two-dimensional analytical Tunnel-FET model is revised. It is used to evaluate performance enhancing measures for the TFET regarding device geometry and physical effects. The usage of hetero-junctions is (...)


Impact of Non-idealities on the Performance of InAs/(In)GaAsSb/GaSb Tunnel FETs

Measured InGaAsSb/InAs nanowire TFETs showing both, sub-60mV/dec slope and high ON-current, are simulated using calibrated TCAD. The focus is laid on the impact of non-idealities, such as hetero-interface traps, (...)


Simulation of 2D material-based tunnel field-effect transistors: planar vs. vertical architectures

Thanks to their thinness, self-passivated surface and large variety, two-dimensional materials have attracted much interest for their possible application in nanoelectronics. In particular, semiconducting transition metal (...)


SiGe based line tunneling field-effect transistors

In this paper we report on our progress with SiGe gate-normal / line tunneling FETs, highlighting recent advancements by the example of three transistor concepts. We demonstrate the unique characteristics shared by these (...)


Editorial Board


Editor in Chief

Francis BALESTRA
CNRS-Grenoble INP-Minatec
francis.balestra@imep.grenoble-inp.fr


Co-Editors

Frédéric ALLIBERT
SOITEC, Grenoble
frederic.allibert@soitec.com

Robert BAPTIST
LETI-CEA, Grenoble
robert.baptist@cea.fr

Olivier THOMAS
LETI-CEA, Grenoble
olivier.thomas@cea.fr
 


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