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Vol 1 - Tunnel FETs

Composants nanoélectroniques

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FET à effet Tunnel pour les Nanocomposants ultra basse puissance

Future ICs are facing dramatic challenges in performance as well as static and dynamic power consumption, which could be overcome using disruptive concepts, device architectures, technologies and materials. Promising solutions includes III-V channels, heterojunctions, 2D (...)

Effets limitant la performance des FET Tunnel

In this paper a two-dimensional analytical Tunnel-FET model is revised. It is used to evaluate performance enhancing measures for the TFET regarding device geometry and physical effects. The usage of hetero-junctions is discussed and a way to suppress the ambipolar behavior (...)

Impact des non-idéalités sur les performances des FET Tunnel InAs / (In)GaAsSb / GaSb

Measured InGaAsSb/InAs nanowire TFETs showing both, sub-60mV/dec slope and high ON-current, are simulated using calibrated TCAD. The focus is laid on the impact of non-idealities, such as hetero-interface traps, oxide-interface traps, and bulk traps on device (...)

Simulation de transistors à effet de champ tunnel à base de matériaux 2D : architectures planaires vs. verticales

Thanks to their thinness, self-passivated surface and large variety, two-dimensional materials have attracted much interest for their possible application in nanoelectronics. In particular, semiconducting transition metal dichalcogenides and their van der Waals (...)

Transistors à effet de champ SiGe à effet tunnel linéaire

In this paper we report on our progress with SiGe gate-normal / line tunneling FETs, highlighting recent advancements by the example of three transistor concepts. We demonstrate the unique characteristics shared by these transistors, such as the on-current proportionality to (...)

Influence de la température sur les nTFETs In0.53Ga0.47As

In this paper, a comparative study between the use of spin on glass and gas phase Zn diffusion of the p++ source of InGaAs TFETs was performed. The use of Zn gas phase doping at the source reduces the tunneling length which results in an enhancement of ION, higher transistor (...)

Modélisation quantique des architectures tunnel-FET III-V

This paper review the device and circuit performance of co-optimized n- and p-type tunnel field-effect transistors (TFETs) integrated on the same InAs/Al0.05Ga0.95Sb platform, using a full-quantum ballistic simulator. Based on 3D full-quantum simulations, the investigated (...)

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Volume 18- 1

Tunnel FETs


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