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Future ICs are facing dramatic challenges in performance as well as static and dynamic power
consumption, which could be overcome using disruptive concepts, device architectures, technologies and materials. Promising solutions includes III-V channels, heterojunctions, 2D layers, multi-gates structures, nanowires (NWs), tunnel FETs (TFETs), ferroelectric FETs (Fe-FETs), and hybrid devices. In the domain of small slope switches, which are very interesting for ultra low power operation, TFETs, Fe-FETs and hybrid devices seem very promising. Thus far, no one has experimentally demonstrated a TFET that has simultaneously both a CMOS-competitive driving current Ion and a sub-60 mV/decade subthreshold swing over several decades. But recently, substantial improvements of TFET and hybrid device performance have been reported, showing that these novel device architectures using new materials and carrier transport could be used for several applications.
In this paper a two-dimensional analytical Tunnel-FET model is revised. It is used to evaluate performance enhancing measures for the TFET regarding device geometry and physical effects. The usage of hetero-junctions is discussed and a way to suppress the ambipolar behavior of the TFET is shown. In focus of this work are the emerging variability issues with this new type of device. Random-dopant-fluctuations (rdf) have a major influence on the device performance. This effect is analyzed and compared with rdf effects in a MOSFET device. The drawn conclusions lead to a
re-evaluation of performance limiting aspects of fabricated TFET devices.
Measured InGaAsSb/InAs nanowire TFETs showing both, sub-60mV/dec slope and high ON-current, are simulated using calibrated TCAD. The focus is laid on the impact of non-idealities, such as hetero-interface traps, oxide-interface traps, and bulk traps on device characteristics. Simulated temperature-dependent transfer curves are in good agreement with the measured data which validates the simulation set-up. It is found that trap-assisted tunneling involving bulk traps adjacent to the hetero-junction is primarily responsible for the degradation of the swing. Due to the small diameter of the nanowire, trap-assisted tunneling is inhibited at the InAs/oxide interface. Still, oxide interface traps reduce the electrostatic coupling between gate and channel, which further increases the swing. The TCAD analysis correctly predicts the negative transconductance observed at high gate bias. If the same simulation set-up is used to study the effect of gate alignment, a significant improvement of both ON-current and swing is found.
Thanks to their thinness, self-passivated surface and large variety, two-dimensional materials have
attracted much interest for their possible application in nanoelectronics. In particular, semiconducting transition metal dichalcogenides and their van der Waals heterostructures are very promising for the realization of low-power tunnel fieldeffect transistors. By means of self-consistent quantum transport simulations, we explore the performances of two alternative architectures for the devices: the planar architecture and the vertical architecture. While for the former, which is based on a p-i-n junction, the tunneling occurs laterally within the same two-dimensional material layer, in the latter the tunneling occurs through the vertical heterostructure between two different materials, which are chosen to have a convenient band alignment. Our results enable a comparison of the performance of two architectures in the ideal case, and can serve as a first guide for the choice of the transistor design based on the desired application.
In this paper we report on our progress with SiGe gate-normal / line tunneling FETs, highlighting recent advancements by the example of three transistor concepts. We demonstrate the unique characteristics shared by these transistors, such as the on-current proportionality to the source-gate-channel overlap area and explain the obstacles imposed by fringing fields leading to parasitic tunneling at the edges of the tunneling area. Our experimental results show that adding counter doping to the channel provides an efficient means to mitigate penalties to the subthreshold swing
caused by parasitic tunneling paths and additionally helps to improve the on-current and Ion/Ioff-ratio. Moreover, we point out the dependence of the superlinear onset on the tunneling transmission probability with a focus on the doping profile at the tunneling junction. We consider the role of traps on the subthreshold swing within the scope of temperature dependent electrical measurements. Furthermore, we show that by avoiding ion implantation and hence crystal defects as much as possible, smaller minimum subthreshold swings can be reached. At last, taking the experience acquired on the three transistors concepts into consideration, we propose an advanced TFET concept.
In this paper, a comparative study between the use of spin on glass and gas phase Zn diffusion of the p++ source of InGaAs TFETs was performed. The use of Zn gas phase doping at the source reduces the tunneling length which results in an enhancement of ION, higher transistor efficiency and intrinsic voltage gain at lower voltages. The main parameters of gas-phased-diffused In0.53Ga0.47As nTFETs with gate stacks composed by 3 nm or 2 nm HfO2 on top of 1 nm Al2O3 have been analyzed. The resulting equivalent oxide thickness (EOT) was about 0.8 nm and 1.0 nm,
respectively. The lower EOT improves the electrostatic coupling, resulting in a lower SS (sub 60 mV/dec at room temperature) leading to a higher gm/IDS in weak conduction. TCAD simulations have shown that the ambipolar effect is significant for higher VDS, degrading SS and consequently gm/IDS in the weak conduction regime, also shifting the gm/IDS peak to higher VGS direction due to the increase of IOFF. The AV peak is strongly degraded by an increase of the temperature due to the increase of the trap-assisted-tunneling (TAT) and Shockley-Read-Hall (SRH) generation
mechanisms. For higher VGS the AV is lower, and at the same time less sensitive to temperature variations, which is a favorable regime for temperature-dependent analog operation.
This paper review the device and circuit performance of co-optimized n- and p-type tunnel field-effect transistors (TFETs) integrated on the same InAs/Al0.05Ga0.95Sb platform, using a full-quantum ballistic simulator. Based on 3D full-quantum simulations, the investigated devices feature steep subthreshold slopes and relatively high ON-state currents, and are combined to realize an inverter. Benchmarking against aggressively scaled CMOS logic based on multigate architectures highlights the potential of the proposed TFET implementations to perform up to 10× and 100× faster for IOFF = 5nA/um and 10 pA/um, respectively, at very low supply voltage VDD = 0.25V, for equal levels of static power dissipation. Afterwards, a simulation study on the impact of interface traps and strain on the I–V characteristics is carried out, in order to capture the effect of interface/border traps on the device electrostatics. The effect of an experimental Dit distribution of a high-k gate stack on InAs is investigated. Unfortunately, traps induce a significant reduction of the ON-state current. However, it turns out that localized strain at the source/channel heterojunction caused by lattice mismatch is able to induce a performance enhancement for the n-type TFET, with respect to the ideal device, even in the presence of traps. On the contrary, for the p-type one, a current degradation 18% is observed.
